VLIW (Very Long Instruction Word) processors and superscalar processors are processors known for achieving enhanced processing performance through simultaneous execution of a plurality of instructions.
FIG. 1 is a diagram schematically illustrating the configuration of a prior art VLIW processor. The VLIW processor 900 includes a fetch unit 902 which fetches a VLIW instruction from an instruction memory 901 in an instruction fetch stage (IF), decoders 911 to 914 which decode the VLIW instruction into a plurality of arithmetic-logic instructions in an instruction decode stage (ID), a plurality of arithmetic-logic units (ALUs) 921 to 924 which execute the plurality of arithmetic-logic instructions in an execution stage (EX), and a register 930 which holds the results of the operations in a writeback stage (WB).
FIG. 2 is a diagram schematically illustrating the configuration of a prior art superscalar processor. The superscalar processor 940 includes an instruction dispatcher 941 between the instruction fetch stage and the instruction decode stage. The instruction dispatcher 941 dynamically changes the number of instruction executions and the assignment of instructions to the arithmetic-logic units 921 to 924 in accordance with the usage conditions of the arithmetic-logic units 921 to 924.
Following patent document 1 discloses a data processing apparatus in which a plurality of data paths capable of operating independently of each other are formed using a plurality of processing units whose input/output interfaces are reconfigurable.
Patent document 1: Japanese Unexamined Patent Publication No. 2004-102988